Leon's Eclectic Blog

I pre-ordered one of the new Raspberry PI Pico 2 boards as soon as they were announced a few days ago. I saw that Pimoroni had their own similar board, the Pico Plus 2, available so I ordered one of those and received it a couple of days later. I had it flashing its LED in a few minutes. The Pimoroni board has several advantages over the Raspberry Pi unit, like more memory, but costs over twice as much. This is what it looks like:

This board from Chinese company Sipeed uses a Gowin FPGA from their top of the range Arora V 22nm family - the  GW5A-LV25MG121 - mounted on a tiny plug-in module with an SPI flash memory chip. The module plugs into a dock board fitted with a 40-pin connector and three 12-way sockets. The 40-pin connector is intended for an SRAM board and the 12-way sockets take PMOD modules. They are connected directly to the FPGA so they can be used as general I/O. Sipeed also sells a kit with a selection of PMOD modules and an SRAM board. You can buy the board and PMOD kit here:  https://a.aliexpress.com/_EQqvF4N A very simple piece of VHDL code that can be used on the Tang Primer 25K enabling an onboard LED to be controlled with one of the buttons. Useful if you want to try out the board without one of the PMOD modules. Uses button S1 and DONE LED. VHDL code (I called the file led_btn.vhd) library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity led_btn is     Port ( btn : in  STD_LOGIC;       

I used ChatGPT to convert Verilog file Blink_LED.v mentioned in my Sipeed Tang Nano 20K post to VHDL - see the post. It compiled OK but the resultant netlist wouldn't place and route with the Verilog constraints files. All I had to do was change 'clk' to ''sys_clk' in both files. I don't know why ChatGPT changed 'clk' to 'sys_clk' when it generated the VHDL. I thought that clk might be a reserved word in VHDL but ChatGPT said it wasn't! The chip programmed OK with the bitstream (probably the same as the Verilog one) and the LED is flashing at the same rate. I don't know how well ChatGPT will cope with larger programs.

Psychologists at Reading University submitted answers generated by ChatGPT to degree level exam questions and had them marked: https://www.reading.ac.uk/news/2024/Research-News/AI-generated-exam-answers-go-undetected-in-real-world-blind-test Nearly all the answers went undetected and got decent grades! I wish ChatGPT had been around when I did my psychology degree!

Sipeed in China produces a range of little low-cost DIL modules using Gowin FPGAs. They are available via AliExpress. The 20K costs about £26 and contains a GW2AR-18 QN88  device: https://wiki.sipeed.com/hardware/en/tang/tang-nano-20k/nano-20k.html I ordered one about a week ago and it was delivered by Evri this morning. I connected it to my laptop using the supplied USB cable and the orange LEDs lit up in sequence continuously indicating that it was working.  I downloaded a Verilog file which simply blinked one LED at 1 Hz, the associated physical constraints file and the timing constraints file. The Verilog is compiled to produce a netlist that is placed and routed, generating a bitstream that is downloaded into the chip.  Here's the Verilog file (Blink_LED.v):  module led (     input   sys_clk,     input   sys_rst_n,     // reset input     output  reg led        // LED ); reg [23:0] counter;        //定义一个变量来计数 always @(posedge sys_clk or negedge sys_rst_n) begin // Counter block