Button-controlled LED for Sipeed Tang Primer 25K FPGA board

This board from Chinese company Sipeed uses a Gowin FPGA from their top of the range Arora V 22nm family - the GW5A-LV25MG121 - mounted on a tiny plug-in module with an SPI flash memory chip. The module plugs into a dock board fitted with a 40-pin connector and three 12-way sockets. The 40-pin connector is intended for an SRAM board and the 12-way sockets take PMOD modules. They are connected directly to the FPGA so they can be used as general I/O.

Sipeed also sells a kit with a selection of PMOD modules and an SRAM board.

You can buy the board and PMOD kit here: 

https://a.aliexpress.com/_EQqvF4N
A very simple piece of VHDL code that can be used on the Tang Primer 25K enabling an onboard LED to be controlled with one of the buttons. Useful if you want to try out the board without one of the PMOD modules.

Uses button S1 and DONE LED.

VHDL code (I called the file led_btn.vhd)

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity led_btn is
    Port ( btn : in  STD_LOGIC;
           led : out STD_LOGIC);
end led_btn;

architecture Behavioral of led_btn is
begin
    led <= not btn;
end Behavioral;

Physical constraints (I called the file led_btn.cst)

IO_LOC "led" D7;
IO_LOC "btn" H11;
IO_PORT "btn" PULL_MODE=DOWN BANK_VCCIO=3.3;
.
You need to enable the DONE LED:

In Gowin IDE check this
Project -> Configuration -> Place & Route -> Dual-Purpose Pin

Comments

Post a Comment

Popular posts from this blog

Sipeed Tang Nano 20K FPGA board

Image
Sipeed in China produces a range of little low-cost DIL modules using Gowin FPGAs. They are available via AliExpress. The 20K costs about £26 and contains a GW2AR-18 QN88  device: https://wiki.sipeed.com/hardware/en/tang/tang-nano-20k/nano-20k.html I ordered one about a week ago and it was delivered by Evri this morning. I connected it to my laptop using the supplied USB cable and the orange LEDs lit up in sequence continuously indicating that it was working.  I downloaded a Verilog file which simply blinked one LED at 1 Hz, the associated physical constraints file and the timing constraints file. The Verilog is compiled to produce a netlist that is placed and routed, generating a bitstream that is downloaded into the chip.  Here's the Verilog file (Blink_LED.v):  module led (     input   sys_clk,     input   sys_rst_n,     // reset input     output  reg led        // LED ); reg [23:0] counter;        //定义一个变量来计数 always @(posedge sys_clk or negedge sys_rst_n) begin // Counter block
Read more

I nearly died at Easter! Warning - somewhat revolting!

The night before Good Friday I developed a complete intestinal obstruction caused by a stricture which I've had for about five years - it's a common complication of Crohn's disease. I often get partial obstructions which clear in a few hours, sometimes two or three times a week. They are quite painful but this was something else - the pain was unbelievable! I also started vomiting. I knew it was serious so I dialed 999 and an ambulance arrived within about 20 minutes. This was at 02:00 in the middle of the night. My downstairs neighbour let them in and when they arrived I was sitting on the toilet and vomiting at the same time! I couldn't walk down the stairs and the paramedics refused to carry me down because they said it would be too dangerous so I had to shuffle down four flights of stairs on my bottom! I grabbed my phone before we left. Once on the ground floor they put me in a wheelchair and took me to the ambulance. They checked me over and took me to A and E at t
Read more